Method Of Fabricating A Semiconductor Wafer Including A Through Substrate Via (TSV) And A Stepped Support Ring On A Back Side Of The Wafer

ABSTRACT

A semiconductor wafer having a plurality of through substrate vias (TSVs) is disclosed. The semiconductor wafer includes a stepped support ring on an outer edge of the semiconductor wafer, a usable back side region of the semiconductor wafer substantially enclosed by the stepped support ring, and the plurality of TSVs extending from a front side of the semiconductor wafer to the usable back side region of the semiconductor wafer. The stepped support ring includes a step between an outer ring and an inner ring of the stepped support ring. The semiconductor wafer further includes a back side metal on the usable back side region of the semiconductor wafer, a plurality of semiconductor devices on the front side of the semiconductor wafer, where at least one of the plurality of semiconductor devices is coupled to the back side metal through at least one of the plurality of TSVs.

RELATED APPLICATIONS

The present application is a divisional of U.S. application Ser. No.14/794,032 filed Jul. 8, 2015 entitled “Method of Fabricating aSemiconductor Wafer Including a Through Substrate Via (TSV) and aStepped Support Ring on a Back Side of the Wafer” (as amended), whichclaims the benefit of and priority to provisional patent applicationentitled “Thinned Processed Wafer Having Devices and Vias and Method forFormation,” Application Ser. No. 62/036,771 filed on Aug. 13, 2014. Thedisclosures of both applications are hereby incorporated fully byreference into the present application.

FIELD OF THE INVENTION

Semiconductor devices, such as complementary-metal-oxide semiconductor(CMOS) devices, complementary bipolar CMOS (BiCMOS) devices, bipolarjunction transistors (BJTs) and field effect transistors (FETs), andmicroelectro-mechanical systems (MEMS) devices, that are fabricated on afront side of a semiconductor wafer, usually require conductivestructures, such as through substrate vias (TSVs), to provide electricalconnection to a back side of the semiconductor wafer. The connection tothe TSVs from the back side of the semiconductor wafer can be made bygrinding the back side using wafer thinning, polish or grindingequipment with an intention of grinding into the TSVs.

According to a conventional wafer thinning approach, a semiconductorwafer is temporarily bonded to a handle wafer using bonding material,such as polymeric material, which requires low temperature processing,for example, under 250-300° C. The semiconductor wafer is ground usingstandard grinding equipment, which grinds the entire diameter of thesemiconductor wafer, thereby reducing the overall thickness across thesemiconductor wafer. After the grinding action, a polish action, such asChemical Mechanical Polishing (CMP), wet etch or plasma etch, isrequired to polish and remove residues from the back side surface. Inthe conventional approach, the thinned semiconductor wafer needs to bedebonded from the handle wafer. The bonding material tends to outgas at200-300° C., thereby limiting high temperature wafer processing. Also,grinding into metallic filler material in the vias within thesemiconductor wafer can lead to destruction of the grinding wheel andcause subsurface damage or even destruction of the semiconductor wafer.In addition, the final polish action, such as CMP, wet etch or plasmaetch, can cause further stress to the thinned semiconductor wafer, whichcan lead to cracking of the semiconductor wafer rendering dies on thesemiconductor wafer unsuitable for further processing. As a result,reducing the depth of the TSVs in thin semiconductor wafers presentsdifficulties. The conventional wafer thinning approach cannot produceshallow TSVs of 300 μm or less.

As semiconductor dies used in electronic products continue to shrink insize, there is a need in the art for high volume manufacturing ofthinned processed semiconductor wafers having devices and TSVs, forexample, in 150 μm or less thickness range, without causing cracking orsubsurface damage to the semiconductor wafer.

SUMMARY

The present disclosure is directed to thinned processed wafer havingdevices and vias and related method, substantially as shown in and/ordescribed in connection with at least one of the figures, and as setforth in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart illustrating a method of forming a semiconductorwafer having one or more through substrate vias (TSVs) according to oneimplementation of the present application.

FIG. 2A illustrates a cross-sectional view of a semiconductor waferhaving one or more TSVs processed in accordance with an initial actionin the flowchart of FIG. 1 according to one implementation of thepresent application.

FIG. 2B illustrates a cross-sectional view of a portion of asemiconductor wafer having one or more TSVs processed in accordance withan intermediate action in the flowchart of FIG. 1 according to oneimplementation of the present application.

FIG. 2C illustrates a cross-sectional view of a semiconductor waferhaving one or more TSVs processed in accordance with an intermediateaction in the flowchart of FIG. 1 according to one implementation of thepresent application.

FIG. 2D illustrates a cross-sectional view of a semiconductor waferhaving one or more TSVs processed in accordance with a final action inthe flowchart of FIG. 1 according to one implementation of the presentapplication.

FIG. 3A illustrates a top plan view of a semiconductor wafer having oneor more TSVs according to one implementation of the present application.

FIG. 3B illustrates a top plan view of a portion of a semiconductorwafer having one or more TSVs according to one implementation of thepresent application.

FIG. 3C illustrates a cross-sectional view of a portion of asemiconductor wafer having one or more TSVs according to oneimplementation of the present application.

DETAILED DESCRIPTION

The following description contains specific information pertaining toimplementations in the present disclosure. The drawings in the presentapplication and their accompanying detailed description are directed tomerely exemplary implementations. Unless noted otherwise, like orcorresponding elements among the figures may be indicated by like orcorresponding reference numerals. Moreover, the drawings andillustrations in the present application are generally not to scale, andare not intended to correspond to actual relative dimensions.

FIG. 1 shows a flowchart illustrating an exemplary method of fanning asemiconductor wafer having one or more TSVs according to animplementation of the present inventive concepts. Certain details andfeatures have been left out of flowchart 100 that are apparent to aperson of ordinary skill in the art. For example, an action may consistof one or more subactions or may involve specialized equipment ormaterials, as known in the art. Actions 180 through 186 indicated inflowchart 100 are sufficient to describe one implementation of thepresent inventive concepts, other implementations of the presentinventive concepts may utilize actions different from those shown inflowchart 100. Moreover, structures 280, 282, 284 and 286 in FIGS. 2A,2B, 2C and 2D illustrate the results of performing actions 180, 182, 184and 186 of flowchart 100, respectively. For example, structure 280 is anexemplary structure of a portion of a semiconductor wafer afterprocessing action 180, structure 282 is an exemplary structure after theprocessing of action 182, structure 284 is an exemplary structure afterthe processing of action 184, and so forth.

Referring to action 180 in FIG. 1 and structure 280 in FIG. 2A, action180 of flowchart 100 includes forming one or more TSVs and one or moredevices on a front side of a semiconductor wafer. As illustrated in FIG.2A, structure 280 includes semiconductor wafer 202, TSVs 208 a, 208 b,208 c, 208 d, 208 e, 208 f, 208 g, 208 h, 208 i and 208 j (hereinaftercollectively referred to as “TSVs 208 a through 208 j”), and devices 210a, 210 b, 210 c, 210 d, 210 e, 210 f, 210 g, 210 h, 210 i, 210 j, 210 k,2101, 210 m, 210 n and 210 o (hereinafter collectively referred to as“devices 210 a through 210 o”), after completion of action 180 offlowchart 100 in FIG. 1.

As illustrated in FIG. 2A, semiconductor wafer 202 includes front side204 and back side 206. In an implementation of the present application,semiconductor wafer 202 may be a group IV wafer, such as silicon,silicon germanium, germanium, or the like. In another implementation,semiconductor wafer 202 may include interlayer dielectric layers andinterconnect metal layers (not explicitly shown in FIG. 2A). TSVs 208 athrough 208 j are formed on front side 204 of semiconductor wafer 202.For example, TSVs 208 a through 208 j may be fanned by depositing andpatterning a hard mask on front side 204 of semiconductor wafer 202,etching front side 204 to form one or more vias or trenches insemiconductor wafer 202, and filling the one or more vias or trencheswith a metallic filler. In the present implementation, the metallicfiller of TSVs 208 a through 208 j includes tungsten, since tungsten ismore closely matched to silicon with respect to coefficients of thermalexpansion (CTE) than other suitable metallic filler material. In otherimplementations, the metallic filler of TSVs 208 a through 208 j mayinclude other suitable electrically and/or thermally conductivematerial, such as copper and/or titanium.

As illustrated in FIG. 2A, structure 280 further includes devices 210 athrough 210 o formed on front side 204 of semiconductor wafer 202. Inone implementation, one or more devices 210 a through 210 o may includeactive semiconductor devices, such as CMOS devices, BiCMOS devices, BJTsand FETs. In another implementation, one or more devices 210 a through210 o may include passive devices, such as resistors, capacitors andinductors. In yet another implementation, one or more devices 210 athrough 210 o may include MEMS devices or any combination of MEMSdevices, active semiconductor devices and passive devices.

In the present implementation, semiconductor wafer 202 has thickness 203of approximately 725 μm. However, thickness 203 of semiconductor wafer202 is not so limited and may have a thickness outside this range,according to the requirements of a particular application. Also, in thepresent implementation, semiconductor wafer 202 has diameter 205 ofapproximately 200 mm. However, diameter 205 of semiconductor wafer 202is not so limited and may have a diameter outside this range, accordingto the requirements of a particular application.

Referring to action 182 in FIG. 1 and structure 282 in FIG. 2B, action182 of flowchart 100 includes coarse grinding a back side of asemiconductor wafer, for example, by using a coarse grinding wheel toform an outer ring of a stepped support ring. As illustrated in FIG. 2B,structure 282 includes semiconductor wafer 202, TSVs 208 a through 208j, devices 210 a through 210 o, and outer ring 214 on an outer edge ofsemiconductor wafer 202, after completion of action 182 of flowchart 100in FIG. 1.

As illustrated in FIG. 2B, in structure 282, semiconductor wafer 202 instructure 280 is flipped upside down, such that front side 204, havingTSVs 208 a through 208 j and devices 210 a through 210 o, is now at thebottom. In tum, back side 206 is facing up for back side processing. Itis noted that only devices 210 a and 210 b of devices 210 a through 210o are labeled in FIGS. 2B-2D, to preserve visual clarity. During theback side wafer processing and subsequent processing actions, aprotective coating layer (not explicitly shown in FIGS. 2B-2D), can beapplied to front side 204 to protect the front side wafer surface, TSVs208 a through 208 j and devices 210 a through 210 o. The protectivecoating layer may include a thick resist, such as polymethylmethacrylate(PMMA) or polymethylglutarimide (PMGI), or polyimide, which may beformed by spin coating and baking, for example.

As illustrated in FIG. 2B, coarse grinding wheel 211 is utilized tocoarse grind and remove a portion of semiconductor wafer 202 from backside 206. For example, the coarse grind terminates on first interiorsurface 212 of semiconductor wafer 202 at depth 213 below back side 206.In the present implementation, depth 213 is approximately 600-615 μm.However, depth 213 is not so limited and may have a depth outside thisrange, according to the requirements of a particular application.

As further illustrated in FIG. 2B, it is important to note that thecoarse grinding of back side 206 in action 182 terminates on firstinterior surface 212 before reaching TSVs 208 a through 208 j. It isalso important to note that the coarse grinding of back side 206 inaction 182 does not grind the entire diameter of semiconductor wafer 202from back side 206. Instead, it leaves outer ring 214 on the outer edgeof semiconductor wafer 202. As such, at least a portion of outer ring214 retains full thickness 203 of semiconductor wafer 202, as outer ring214 is rounded toward the outer edge of semiconductor wafer 202.

In the present implementation, width 215 of outer ring 214 isapproximately 2-3.5 mm. However, width 215 of outer ring 214 is not solimited and may have a width outside this range, according to therequirements of a particular application. For example, in oneimplementation, it may be desirable to make width 215 as small aspossible to maximize a usable back side region of semiconductor wafer202, while maintaining the structural integrity of semiconductor wafer202.

In contrast to conventional wafer thinning methods, in which the entirebackside of a semiconductor wafer is ground to create a “knife edge”around the semiconductor wafer, the formation of outer ring 214 havinground edge can advantageously avoid edge chipping during wafer thinningand during any subsequent processing actions. Also, after performingaction 182 of flowchart 100, since outer ring 214 forms a rigid framestructure on the outer edge of semiconductor wafer 202 to providemechanical strength to maintain the structural integrity of structure282, structure 282 can be picked up and moved around by hand withoutusing any special wafer handling and/or supporting tools.

Referring to action 184 in FIG. 1 and structure 284 in FIG. 2C, action184 of flowchart 100 includes fine grinding a back side of asemiconductor wafer, for example, by using a fine grinding wheel to forman inner ring of a stepped support ring, and to form a usable back sideregion of the semiconductor wafer substantially enclosed by the steppedsupport ring. Moreover, the fine grinding of the back side of thesemiconductor wafer in action 184 also exposes one or more TSVs in thesemiconductor wafer. As illustrated in FIG. 2C, structure 284 includessemiconductor wafer 202, TSVs 208 a through 208 j, devices 210 a through210 o, outer ring 214, inner ring 218 and usable back side region 224 onback side 206 of semiconductor wafer 202, after completion of action 184of flowchart 100 in FIG. 1.

As illustrated in FIG. 2C, in structure 284, semiconductor wafer 202undergoes a fine grind on back side 206 of semiconductor wafer 202 toform inner ring 218 and usable back side region 224. For example, finegrinding wheel 217 is utilized to fine grind and remove another portionof semiconductor wafer 202 from back side 206. As illustrated in FIG.2C, the fine grind in action 184 terminates on second interior surface216 of semiconductor wafer 202 at depth 219 below back side 206. In thepresent implementation, depth 219 is approximately 625-675 μm. However,depth 219 is not so limited and may have a depth outside this range,according to the requirements of a particular application.

In the present implementation, the fine grind of action 184 of flowchart100 also forms usable back side region 224 from which semiconductor diescan be fabricated. Usable back side region 224 of semiconductor wafer202 has thickness 221. In the present implementation, thickness 221 ofusable back side region 224 is a substantially uniform thickness ofapproximately 100 μm. In another implementation, thickness 221 of usableback side region 224 may be a substantially uniform thickness ofapproximately 50-150 μm. However, thickness 221 of usable back sideregion 224 is not so limited and may have a thickness outside thisrange, according to the requirements of a particular application. Sincethickness 221 of usable back side region 224 is in the 50-150 μm range,for example, it is important that TSVs 208 a through 208 j and devices210 a through 210 o are formed on front side 204 of semiconductor wafer202 before the back side processing, such as before action 182 offlowchart 100.

As illustrated in FIG. 2C, the fine grind does not grind the entirediameter of outer ring 214. Instead, it forms inner ring 218 betweenusable back side region 224 and outer ring 214. Thus, inner ring 218 andouter ring 214 together form stepped support ring 222, where steppedsupport ring 222 includes step 220 between inner ring 218 and outer ring214. As further illustrated in FIG. 2C, stepped support ring 222substantially encloses usable back side region 224. Inner ring 218 isconfigured to further provide mechanical strength to maintain thestructural integrity of structure 284 as semiconductor wafer 202undergoes the fine grind in action 184 of flowchart 100. In the presentimplementation, width 223 of inner ring 218 is a substantially uniformwidth of approximately 1 mm. However, width 223 of inner ring 218 is notso limited and may have a width outside this range, according to therequirements of a particular application. For example, in oneimplementation, it may be desirable to make width 223 as small aspossible to maximize usable back side region 224, while maintaining thestructural integrity of semiconductor wafer 202.

As mentioned above, after the fine grind of action 184, usable back sideregion 224 of semiconductor wafer 202 is thinned to thickness 221 ofapproximately 50-150 μm, for example. Inner ring 218 provides atransition necessary to reduce the stress concentrated at the boundarybetween usable back side region 224 and outer ring 214 to avoid wafercracking during the fine grind of action 184. Without inner ring 218providing the transition between usable back side region 224 and outerring 214, one or more sharp edges would have been resulted between outerring 214 and usable back side region 224. The fine grinding wouldintroduce additional stress to the semiconductor wafer at the sharpedges, which can lead to cracking of the semiconductor wafer.

During the fine grind in action 184 of flowchart 100, it may bedesirable to form second interior surface 216 with a desired amount ofroughness or friction for a deposition of a back side metal in asubsequent action. In order to accomplish the desired amount ofroughness on second interior surface 216, in one implementation of thepresent application, fine grinding wheel 217 includes a finer wheel ascompared to coarse grinding wheel 211 shown in FIG. 2B. In addition,fine grinding wheel 217 may operate at a grinding rate equal to ordifferent from that of coarse grinding wheel 211. Moreover, an automaticfeedback may be implemented in fine grinding wheel 217, such that finegrinding wheel 217 may sense a change in grinding rate when it reachesone or more TSVs 208 a through 208 j during the fine grind in action184.

Upon sensing a change in grinding rate, fine grinding wheel 217 isconfigured to stop grinding after a predetermined time, such that thefine grind in action 184 removes the least amount of metallic filler inone or more TSVs 208 a through 208 j. As a result of the automaticfeedback, the fine grind in action 184 can advantageously minimize thesurface and/or subsurface damage to second interior surface 216. Also,by implementing the automatic feedback during the fine grind inaction184, second interior surface 216 can have the desired amount ofroughness to improve adhesion between second interior surface 216 and aback side metal to be subsequently deposited thereon. In addition, theability to sense a change in grinding rate can minimize damage to andavoid destruction of the grinding wheel, which would otherwise resultfrom the friction between the metallic filler in the TSVs and thegrinding wheel, thus prolonging the lifetime of the grinding wheel.

Without the ability to sense a change in grinding rate, a grinding wheelwould grind into and remove, for example, the metallic filler in one ormore TSVs. The metallic filler, such as tungsten, can be a hard materialas compared to the material in the surrounding semiconductor wafer. Themetallic filler broken off from the one or more TSVs would ramble acrossthe wafer surface as the grinding wheel continues to grind down thewafer. This would result in substantial surface and subsurface damage tothe wafer, and would also lead to cracking of the wafer. Furthermore,without the ability to sense a change in grinding rate, conventionalgrinding methods require a polish action, such as CMP, wet etch andplasma etch, to polish the damaged wafer surface and remove residuesfrom the wafer surface after the grinding action. The polish action canfurther introduce stress to the semiconductor wafer, in addition to thesurface/subsurface damage done to the semiconductor wafer during thegrinding action, which can lead to destruction of the entiresemiconductor wafer.

As a result of the automatic feedback during the fine grind in action184, fine grinding of semiconductor wafer 202 may automaticallyterminate after sensing a change in grinding rate upon reaching one ormore TSVs 208 a through 208 j to minimize damage to second interiorsurface 216. As such, the polishing action required by conventionalwafer thinning approaches can be advantageously avoided.

Referring to action 186 in FIG. 1 and structure 286 in FIG. 2D, action186 includes forming a back side metal on a usable back side region of asemiconductor wafer, where the back side metal is in electrical and/orthermal connection with one or more TSVs. As illustrated in FIG. 2D,structure 286 includes semiconductor wafer 202, TSVs 208 a through 208j, devices 210 a through 210 o, outer ring 214, inner ring 218 and backside metal 226 on usable back side region 224 of semiconductor wafer202, after completion of action 186 of flowchart 100 in FIG. 1.

As illustrated in FIG. 2D, in structure 286, back side metal 226 isformed on usable back side region 224 of semiconductor wafer 202. Backside metal 226 may be formed by using the same material as the materialused for the metallic filler of TSVs 208 a through 208 j. In the presentimplementation, back side metal 226 includes tungsten, as tungsten ismore closely matched to silicon with respect to coefficients of thermalexpansion (CTE) than other suitable materials. In anotherimplementation, back side metal 226 may include other metallic material,such as copper, titanium, or any other suitable electrically and/orthermally conductive material. One or more TSVs 208 a through 208 j canbe utilized to provide electrical and/or thermal connections between oneor more devices 210 a through 210 o and back side metal 226 in anydesired manner. In the present implementation, one or more TSVs 208a-208 j are electrically connected to back side metal 226, which may bea ground plate for semiconductor wafer 202. In another implementation,one or more TSVs 208 a-208 j may be through-silicon vias. In yet anotherimplementation, one or more TSVs 208 a-208 j may be isolated TSVs. Asdiscussed above with FIGS. 1 and 2A through 2D, implementations of thepresent inventive concepts can achieve a thinned processed wafer withone or more TSVs that extends through the thinned processed wafer havinga thickness of approximately 50-150 μm.

FIG. 3A presents a top plan view of an exemplary semiconductor wafer,according to an implementation of the present application. Inparticular, exemplary structure 300 of FIG. 3A shows a top plan view ofback side 306 of semiconductor wafer 302 having stepped support ring322. Semiconductor wafer 302 includes front side 304 (not explicitlyshown in FIG. 3A) and back side 306. As illustrated in FIG. 3A, on backside 306 of semiconductor wafer 302, usable back side region 324 issubstantially enclosed by stepped support ring 322. Stepped support ring322 includes outer ring 314 and inner ring 318. Semiconductor wafer 302also includes a plurality of TSVs, semiconductor devices and othercircuit elements on front side 304 of semiconductor wafer 302 (notexplicitly shown in FIG. 3A). In an implementation of the presentapplication, semiconductor wafer 302 may be a group IV wafer, such assilicon, silicon germanium, germanium, or the like. In anotherimplementation, semiconductor wafer 302 may include interlayerdielectric layers and interconnect metal layers (not explicitly shown inFIG. 3A).

FIG. 3B presents a magnified top plan view of a region of an exemplarysemiconductor wafer shown in FIG. 3A, according to an implementation ofthe present application. In particular, FIG. 3B illustrates a magnifiedtop plan view of region 330 of semiconductor wafer 302 in FIG. 3A, whereregion 330 includes portions of stepped support ring 322 and usable backside region 324, for example.

FIG. 3C presents a cross-sectional view of a region of an exemplarysemiconductor wafer, according to an implementation disclosed in thepresent application. In particular, FIG. 3C illustrates across-sectional view of region 330 of semiconductor structure 300 ofFIG. 3A along the line C-C′ shown in FIG. 3B. As illustrated in FIG. 3C,semiconductor wafer 302 includes front side 304 and back side 306.Devices 310 a, 310 b, 310 c, 310 d, 310 e, and 310 f (hereinaftercollectively referred to as ‘devices 310 a through 310 f”) are formed onfront side 304 of semiconductor wafer 302. In an implementation, one ormore devices 310 a through 310 f may include active semiconductordevices, such as CMOS devices, BiCMOS devices, BJTs and FETs. In anotherimplementation, one or more devices 310 a through 310 f may includepassive devices, such as resistors, capacitors and inductors. In yetanother implementation, one or more devices 310 a through 310 f mayinclude MEMS devices or any combination of MEMS devices, activesemiconductor devices and passive devices.

As illustrated in FIG. 3C, TSVs 308 a, 308 b, 308 c and 308 d(hereinafter collectively referred to as “TSVs 308 a through 308 d”) arealso fanned on front side 304 of semiconductor wafer 302 prior to a backside wafer process. One or more TSVs 308 a through 308 d may be utilizedto provide electrical and/or thermal connections between one or moredevices 310 a through 310 f and a back side metal (not explicitly shownin FIG. 3C) on back side 306 of semiconductor wafer 302 in any desiredmanner. In one implementation, one or more TSVs 308 a through 308 d maybe through-silicon vias connected to a ground plate or patterns of oxideor metal interconnects on semiconductor wafer 302. In anotherimplementation, one or more TSVs 308 a through 308 d may be isolatedTSVs.

As further illustrated in FIG. 3C, semiconductor wafer 302 includesstepped support ring 322 on an outer edge thereof, where stepped supportring 322 substantially encloses usable back side region 324. Steppedsupport ring 322 includes step 320 between inner ring 318 and outer ring314. Stepped support ring 322 provides mechanical strength to maintainthe structural integrity of semiconductor wafer 302 during and after theformation of stepped support ring 322, such that, after the formation ofouter ring 314, the wafer process can continue in most tools without theassistance of a temporarily bonded wafer. As such, semiconductor wafer302 having stepped support ring 322 can be picked up and moved around byhand without using any special wafer handling and/or supporting tools.

In the present implementation, semiconductor wafer 302 may have a fullthickness of approximately 725 μm and a diameter of approximately 200 1mn, for example. Usable back side region 324, which may correspond to athinned region of semiconductor wafer 302, may have a thickness ofapproximately 50 μm, 75 μm, 100 μmor 150 μm. A lateral distance betweenTSV 308 a and device 310 b may be approximately 5-10 μm.

The present inventive concepts utilize a stepped support ring having aninner ring and an outer ring to substantially enclose a usable back sideregion of a semiconductor wafer, where the outer ring of the steppedsupport ring is fanned on an outer edge of the semiconductor wafer toprovide mechanical strength to maintain the structural integrity of thesemiconductor wafer during and after the wafer thinning process, and theinner ring of the stepped support ring provides a transition necessaryto reduce the stress concentrated on the boundary between a usable backside region and the outer ring. The present inventive concepts alsoutilizes a two pass grinding process to first coarse grind and remove aportion of the semiconductor wafer from the back side, then fine grindthe back side of the semiconductor wafer using a finer grinding wheelthat is configured to stop the grinding upon reaching the TSVs tominimize mechanical damage to the wafer surface to provide an excellentsurface for further processing. As such, a final polish action, such asCMP, wet etch or plasma etch, in conventional wafer processing methodscan be avoided, thereby saving manufacture cost and time. The presentinventive concepts can also allow higher temperature processing, preventadditional processes from contaminating the wafer surfaces, for example,during bonding and debonding processes, thereby further reducingmanufacture cost and time.

As can be understood by a person of ordinary skill in the art that theprocessed wafer having TSVs can be diced and singulated into individualdies and thereafter packaged using various semiconductor packagingtechniques and processes. As such, the present inventive concepts aremanifestly applicable to fabricating semiconductor wafers and/or dies,which may or may not be later packaged, in accordance with the presentdisclosure described above.

From the above description it is manifest that various techniques can beused for implementing the concepts described in the present applicationwithout departing from the scope of those concepts. Moreover, while theconcepts have been described with specific reference to certainimplementations, a person of ordinary skill in the art would recognizethat changes can be made in form and detail without departing from thescope of those concepts. As such, the described implementations are tobe considered in all respects as illustrative and not restrictive. Itshould also be understood that the present application is not limited tothe particular implementations described above, but many rearrangements,modifications, and substitutions are possible without departing from thescope of the present disclosure.

1. A semiconductor wafer having a plurality of through substrate vias (TSVs), said semiconductor wafer comprising: a stepped support ring on an outer edge of said semiconductor wafer; a usable back side region of said semiconductor wafer substantially enclosed by said stepped support ring; and said plurality of TSVs extending from a front side of said semiconductor wafer to said usable back side region of said semiconductor wafer.
 2. The semiconductor wafer of claim 1, wherein said stepped support ring comprises a step between an outer ring and an inner ring of said stepped support ring.
 3. The semiconductor wafer of claim 1, wherein at least one of said plurality of TSVs comprises tungsten.
 4. The semiconductor wafer of claim 1, further comprising a back side metal on said usable back side region of said semiconductor wafer.
 5. The semiconductor wafer of claim 1, further comprising a plurality of semiconductor devices on said front side of said semiconductor wafer.
 6. The semiconductor wafer of claim 5, wherein at least one of said plurality of semiconductor devices is coupled to a back side metal through at least one of said plurality of TSVs.
 7. A semiconductor wafer having a plurality of devices, said semiconductor wafer comprising: a stepped support ring on an outer edge of said semiconductor wafer, said stepped support ring having a step between an outer ring and an inner ring of said stepped support ring; a usable back side region of said semiconductor wafer substantially enclosed by said stepped support ring; said plurality of devices situated on a front side of said semiconductor wafer.
 8. The semiconductor wafer of claim 7, wherein at least one of said plurality of devices includes an active semiconductor device.
 9. The semiconductor wafer of claim 7, wherein at least one of said plurality of devices includes a passive device.
 10. The semiconductor wafer of claim 7, further comprising a back side metal on said usable back side region.
 11. The semiconductor wafer of claim 10, wherein at least one of said plurality of devices is coupled to said back side metal through at least one through substrate via (TSV). 